DocumentCode :
3264591
Title :
Reconfigurable design with clock gating
Author :
Osborne, W.G. ; Luk, W. ; Coutinho, J. G F ; Mencer, O.
Author_Institution :
Dept. of Comput., Imperial Coll. London, London
fYear :
2008
fDate :
21-24 July 2008
Firstpage :
187
Lastpage :
194
Abstract :
This paper describes an approach for developing energy-optimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable word-length optimization. The conditions under which this approach would be preferable to bit-stream reconfiguration are derived. Various case studies, such as ray tracing, guitar string simulation and matrix-vector multiplication, are used to illustrate this approach.
Keywords :
field programmable gate arrays; reconfigurable architectures; bit-stream reconfiguration; clock gating; energy-optimized run-time reconfigurable designs; guitar string simulation; matrix-vector multiplication; multiplexer-based reconfiguration; ray tracing; reconfigurable word-length optimization; Circuits; Clocks; Current measurement; Delay; Educational institutions; Energy consumption; Field programmable gate arrays; Multiplexing; Ray tracing; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on
Conference_Location :
Samos
Print_ISBN :
978-1-4244-1985-2
Type :
conf
DOI :
10.1109/ICSAMOS.2008.4664863
Filename :
4664863
Link To Document :
بازگشت