One method for designing speed independent logic for a control

Since the design of speed independent logic, like many other synthesis procedures, does not produce a unique topology, a design technique has been developed at Illinois to insure consistency throughout the control. The majority of the logical design problems were presented as information flow charts to be realized. All of the typical sections of flow charts were realized in a speed independent manner and these were used as building block to design the complete control. Speed independent logic is different from other asychronous logic in the use of reply signals to indicate the completion of a given operation. These reply signals are incorporated in the basic sequencing control logic to time operations. In addition to verifying that the desired operation has been performed, the use of replies eliminates the need for model flipflops or timing delays. In addition to the flow chart problems mentioned, basic logical realizations to the following problems were created: a selector control mechanism which would set the desired state and then give a reply; a memory element with a reply signal; and interlock systems to supervise the operation of two otherwise autonomous controls which exchange data.