DocumentCode
3264753
Title
An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder
Author
Takizawa, Tetsuro ; Hirasawa, Masao
Author_Institution
Multimedia Labs., NEC Corp., Japan
fYear
2001
fDate
2001
Firstpage
182
Lastpage
183
Abstract
This paper presents an efficient memory arbitration algorithm for system on a chip. We have implemented the algorithm into a single chip MPEG2 AV decoder. According to simulations, memory access efficiency of the arbiter based on the new algorithm is around 95% with a 32-bit 133 MHz SDRAM, while those of conventional arbiters are less than 80%
Keywords
DRAM chips; asynchronous circuits; audio coding; audio-visual systems; code standards; data compression; decoding; large scale integration; telecommunication standards; video coding; 133 MHz; 32 bit; LSI; MPEG2 video decoding; SDRAM; bus architecture; efficient memory arbitration algorithm; memory access efficiency; simulations; single chip MPEG2 AV decoder; system on a chip; Costs; Decoding; Digital TV; Large scale integration; National electric code; SDRAM; Switches; System buses; US Department of Transportation; Video sharing;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2001. ICCE. International Conference on
Conference_Location
Los Angeles, CA
Print_ISBN
0-7803-6622-0
Type
conf
DOI
10.1109/ICCE.2001.935265
Filename
935265
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