DocumentCode :
3264773
Title :
Real-time hardware implementation of HEVC video encoder for 1080p HD video
Author :
Miyazawa, K. ; Sakate, Hiroharu ; Sekiguchi, Shun-ichi ; Motoyama, Nobuaki ; Sugito, Yasuko ; Iguchi, Kenichi ; Ichigaya, Atsuro ; Sakaida, Shin-ichi
Author_Institution :
Mitsubishi Electr. Corp., Kamakura, Japan
fYear :
2013
fDate :
8-11 Dec. 2013
Firstpage :
225
Lastpage :
228
Abstract :
This paper describes a hardware implementation of HEVC (High Efficiency Video Coding) video encoder for exploring performance of HEVC in real-time applications. By optimizing hardware architecture and developing fast mode decision algorithms, our FPGA-based prototype can encode 1080p, 10-bit video at 60fps in real-time. Both objective and subjective evaluations clearly demonstrate that the developed HEVC encoder achieves significant coding gain relative to professional-use AVC/H.264 encoder available on the market. This paper also refers to the development of a real-time HEVC encoder for much higher resolution video such as SHV (Super Hi-Vision, 8K) using the HD encoder in parallel.
Keywords :
field programmable gate arrays; high definition video; video codecs; video coding; AVC/H.264 encoder; FPGA; HD video; HEVC video encoder; SHV; Super Hi-Vision; coding gain; fast mode decision algorithm; field programmable gate arrays; high definition video; high efficiency video coding; real time hardware implementation; word length 10 bit; Bit rate; Encoding; Hardware; High definition video; Real-time systems; Streaming media; Video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Picture Coding Symposium (PCS), 2013
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4799-0292-7
Type :
conf
DOI :
10.1109/PCS.2013.6737724
Filename :
6737724
Link To Document :
بازگشت