DocumentCode
3264935
Title
An Efficient Architecture of 1024-bits Cryptoprocessor for RSA Cryptosystem Based on Modified Montgomery´s Algorithm
Author
Zhengbing, Hu ; Al Shboul, Rabah Mohd ; Shirochin, V.P.
Author_Institution
Huazhong Normal Univ., Wuhan
fYear
2007
fDate
6-8 Sept. 2007
Firstpage
643
Lastpage
646
Abstract
In this paper, a new architecture using only one carry save adder (CSA) was proposed to implement modular multiplication based on the modified Montgomery modular multiplication algorithm. It can improve the time efficiency of RSA cryptoprocessor and save about half of hardware resources for modular multiplication. With the increase of encryption data size n, the time of the encryption procedure is about n clock cycles which compared with the modular multiplication algorithm using two CSA.
Keywords
adders; cryptography; microprocessor chips; 1024-bits cryptoprocessor; carry save adder; cryptosystem; encryption data; encryption procedure; hardware resources; modified Montgomery modular multiplication algorithm; modular multiplication; Authentication; Clocks; Computer architecture; Conferences; Data acquisition; Data security; Hardware; IP networks; Kernel; Public key cryptography;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2007. IDAACS 2007. 4th IEEE Workshop on
Conference_Location
Dortmund
Print_ISBN
978-1-4244-1347-8
Electronic_ISBN
978-1-4244-1348-5
Type
conf
DOI
10.1109/IDAACS.2007.4488500
Filename
4488500
Link To Document