An accurate low iteration algorithm for effective capacitance computation

This paper presents an efficient and accurate approach to calculate effective capacitances in the presence of RC interconnect loads. In the pre-characterization process, the gate model is selected such that the output of the model matches both the delay and the shape of the real gate response. In order to determine the effective capacitance, a novel algorithm is developed to efficiently and accurately calculate the propagation delay from circuit elements. This algorithm requires at most two iterations to obtain effective capacitances that produce gate delays within 4% of HSPICE results. This is at most half the time required by the currently used method to calculate effective capacitances.