DocumentCode :
32654
Title :
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model
Author :
Zijian He ; Tao Lv ; Huawei Li ; Xiaowei Li
Author_Institution :
State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
Volume :
21
Issue :
7
fYear :
2013
fDate :
Jul-13
Firstpage :
1210
Lastpage :
1219
Abstract :
This paper proposes a test path selection approach for capturing delay failures caused by the accumulated distributed small delay variations. First, a universal path candidate set U, which contains testable long paths, is generated. Second, given a path number threshold, path selection from U is performed with the objective of maximizing the capability to capture potential delay failures. The path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that all the paths in a specified path set meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time efficient and achieves higher probability of capturing delay failures than traditional path selection approaches.
Keywords :
circuit testing; delays; statistical analysis; delay failure; greedy path selection heuristics; minimal space intersection problem; probability; statistical timing analysis; test path selection; testable long path; universal path candidate set; Correlation; Delay; Logic gates; Random variables; Testing; Delay testing; path correlation; statistical timing model; test path selection;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2012.2208661
Filename :
6268362
Link To Document :
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