A programmable clock generator HDL softcore

Author

Eisenreich, H. ; Mayr, C. ; Henker, S. ; Wickert, M. ; Schuffny, Rene

Author_Institution

Univ. of Technol. Dresden, Dresden

fYear

2007

fDate

5-8 Aug. 2007

Firstpage

1

Lastpage

4

Abstract

This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35 um and UMC 0,13 um have been manufactured and tested. Measurements show competitive results to state-of-the- art mixed signal implementations.

Keywords

CMOS integrated circuits; application specific integrated circuits; clocks; digital control; frequency control; hardware description languages; oscillators; programmable circuits; regulation; ADPLL architecture; ASIC; CMOS AMS; HDL softcore; UMC; VHDL; digital controlled oscillator; frequency control; programmable clock generator; robust regulation algorithm; Clocks; Digital control; Digital-controlled oscillators; Frequency control; Hardware design languages; Jitter; Manufacturing; Robust control; Signal resolution; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on

Conference_Location

Montreal, Que.

ISSN

1548-3746

Print_ISBN

978-1-4244-1175-7

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2007.4488528

Filename

4488528