• DocumentCode
    3265506
  • Title

    A fast hardware implementation of multiplicative inversion in GF(2m)

  • Author

    Deng, Qiucheng ; Bai, Xuefei ; Guo, Li ; Wang, Yao

  • Author_Institution
    Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China
  • fYear
    2009
  • fDate
    19-21 Jan. 2009
  • Firstpage
    472
  • Lastpage
    475
  • Abstract
    In this paper, a fast hardware implementation of multiplicative inversion in GF(2m) using the optimal normal basis of type II is presented. The approach followed is based on the Sunar-Koc multiplier and the Itoh-Tsujii algorithm. Our design is able to compute multiplicative inversion in GF(2233) using only 26 clock cycles.
  • Keywords
    Galois fields; clocks; multiplying circuits; GF(2m); Itoh-Tsujii algorithm; Sunar-Koc multiplier; clock cycles; hardware implementation; multiplicative inversion; optimal normal basis; Arithmetic; Books; Clocks; Computer architecture; Elliptic curve cryptography; Galois fields; Hardware; Iterative algorithms; Reed-Solomon codes; Very large scale integration; Optimal normal basis; elliptic curve cryptography; finite field; multiplicative inversion;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-4668-1
  • Electronic_ISBN
    978-1-4244-4669-8
  • Type

    conf

  • DOI
    10.1109/PRIMEASIA.2009.5397344
  • Filename
    5397344
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3265506