A novel power estimation framework for SRAM-based FPGAs

Field programmable gate arrays (FPGAs) is becoming one of the most widely used electronics devices. Because of its unique architecture, power estimation is a complicated task for FPGAs. This paper presents a novel power estimation framework for SRAM-based FPGAs. Considering both dynamic power and static power, a gate-level power model for configuration logic blocks (CLBs) and a transistor-level power model for interconnect resources is developed for power estimation of SRAM-based FPGAs. To achieve the accuracy and efficiency, we use the transition density method includes glitches filtering in our proposed power estimation framework. 20 MCNC benchmark circuits have been applied to our proposed power estimation framework, and the detailed power dissipation distribution obtained from the experimental results is presented. The proposed framework is also quite flexible, which is capable of estimating power for a wide variety of SRAM-based FPGA architectures.