A novel memory architecture for real-time mesh-based video motion compensation

This paper presents a memory architecture for real-time mesh-based video motion compensation. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The reference and current frames are stored in SRAMs generated with Virage™ memory compiler. The proposed architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. At 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e. 352x288 pixels) in 0.59 ms. This means it can process up to 1694 frames per second. The core area of the proposed architecture is 28.04 mm² and its power consumption is 31.15 mW.