Estimating the temperature rise of power MOSFETs during the UIS test

Author

Mcgloin, John ; Sdrulla, Dumitru

Author_Institution

Adv. Power Technol., Bend, OR, USA

fYear

1992

fDate

23-27 Feb 1992

Firstpage

448

Lastpage

453

Abstract

A method for determining the temperature rise of a power MOSFET during an unclamped inductive switching (UIS) test is described. The procedure consists of the following steps: breakdown voltage avalanche resistance measurement, breakdown voltage temperature coefficient calibration, and voltage waveform monitoring during the UIS test. A first-order model of the voltage waveform allows the computation of the junction temperature rise due to self-heating during a high-energy, long-pulse UIS test. The estimations are compared with those obtained based on the thermal impedance concept

Keywords

insulated gate field effect transistors; power transistors; semiconductor device testing; switching circuits; thermal analysis; thermal variables measurement; SDT; breakdown voltage avalanche resistance; breakdown voltage temperature coefficient; calibration; junction; measurement; power MOSFETs; self-heating; semiconductor device testing; temperature rise; thermal analysis; thermal impedance; unclamped inductive switching; voltage waveform monitoring; Breakdown voltage; Circuit testing; Coils; Electrical resistance measurement; Impedance; Inductance; MOSFETs; P-n junctions; Pulse measurements; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 1992. APEC '92. Conference Proceedings 1992., Seventh Annual

Conference_Location

Boston, MA

Print_ISBN

0-7803-0485-3

Type

conf

DOI

10.1109/APEC.1992.228375

Filename

228375