DocumentCode
3265854
Title
Design strategies for ESD protection in SOC
Author
Iniewski, K. ; Axelrad, V. ; Shibkov, A. ; Balasinski, A. ; Syrzycki, M.
Author_Institution
Dept. of ECE, Alberta Univ., Edmonton, Alta., Canada
fYear
2004
fDate
19-21 July 2004
Firstpage
210
Lastpage
214
Abstract
Design strategies for efficient ESD protection in system-on-chip (SOC) integrated circuits are discussed. Various options for power clamp and I/O ESD architectures are considered. Multiple ESD protection circuits with feedback triggering have been analyzed using physical mixed-mode circuit-device simulation, utilizing finite element models for MOSFETs.
Keywords
MOSFET circuits; electrostatic discharge; feedback; integrated circuit design; mixed analogue-digital integrated circuits; protection; system-on-chip; ESD protection circuits; I/O ESD architectures; MOSFET; SOC integrated circuits; electrostatic discharge; mixed-mode circuit-device simulation; system-on-chip; Analytical models; Circuit simulation; Clamps; Electrostatic discharge; Feedback circuits; Finite element methods; MOSFETs; Power system modeling; Power system protection; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Print_ISBN
0-7695-2182-7
Type
conf
DOI
10.1109/IWSOC.2004.1319880
Filename
1319880
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