Accurate on-chip variation modeling to achieve design for manufacturability

Undesired on-chip variations (OCV) become more prominent in scaled technologies. They decrease VLSI/SoC yields even though three design-for-manufacturability (DFM) techniques have been widely adopted by CMOS foundries to enhance the uniformity of copper-based interconnect. A new modeling and DFM analysis methodology is therefore proposed to accurately characterize the OCV from the perspective of circuit parameters rather than from that of process parameters. The resulting OCV is more straightforward and easier to be implemented in the mainstream electronic design automation (EDA) design flows to insure high yields.