Title :
A novel LOP to improve the normalization of the FP adder in DSPs
Author :
JianPing, Fang ; Yue, Hao ; DeLiang, Che
Author_Institution :
Inst. of Microelectron., Xidian Univ., China
Abstract :
This paper presents a novel leading-one predictor (LOP) for an SMDSP extended precision floating-point adder in digital signal processors (DSPs.). The LOP is area-efficient and has less delay overhead. The regular circuit architecture also makes it easy to design and implement in VLSI. In this paper, we mainly describe the structural and logical design of the LOP module that can be applicable to many floating-point adders.
Keywords :
VLSI; adders; digital signal processing chips; floating point arithmetic; DSP adder normalization; LOP module; SMDSP extended precision floating-point adder; VLSI; delay overhead; digital signal processors; leading-one predictor; Acceleration; Adders; Circuits; Delay; Digital signal processing; Digital signal processors; Error correction; Microelectronics; Signal design; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435144
