An novel FDWT and IDWT architecture for JPEG2000

Author

Zhu, Ke ; Wang, Fang ; Zhou, Xiao-Fang ; Zhang, Qian-ling

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

Volume

3

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1641

Abstract

A novel forward and inverse discrete wavelet transformation VLSI architecture for JPEG2000 is proposed. First of all, the reducing scaling coefficients multiplication algorithm (RSCM) was introduced. Then, starting from transform characteristics, the architecture is presented showing both performance and cost. Our implementation is a new architecture that can perform both FDWT and IDWT using filters recommended by JPEG2000. Our architecture has a flexible configuration and high processing speed. The architecture has been implemented in RTL-level Verilog. The estimated number of gates in our proposed architecture in SIMC 0.18-μm technology is 15500 and the estimated frequency of operation is 150 MHz.

Keywords

VLSI; discrete wavelet transforms; image coding; logic circuits; 0.18 micron; 150 MHz; FDWT; IDWT; JPEG2000; RSCM; RTL-level Verilog; VLSI; discrete wavelet transformation; forward DWT; inverse DWT; reducing scaling coefficients multiplication algorithm; Application specific integrated circuits; Costs; Discrete transforms; Discrete wavelet transforms; Filters; Frequency estimation; Hardware design languages; Image coding; Laboratories; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435145

Filename

1435145