Title :
A new 2-D parity checking architecture for radiation-hardened by design SRAM
Author :
Rao, Quan-Lin ; He, Chun
Author_Institution :
Res. Inst. of Electron. Sci. & Technol., Univ. of Electron. & Sci. Technol. of China, Chengdu, China
Abstract :
A novel two-dimension (2-D) parity checking architecture is proposed for radiation-hardened by design (RHBD) SRAMs, which are insensitive to radiation-induced single-event upsets (SEU). The common 2-D parity checking method and its limitations in high density RHBD SRAMs are discussed. The novel architecture, which could be used to correct up to four adjacent upset errors, is more suitable for protecting high density memories from SEU. This novel 2-D parity checking architecture has been successfully used in RHBD SRAMs embedded in a SOC chip.
Keywords :
SRAM chips; integrated circuit design; radiation hardening (electronics); 2D parity checking architecture; SOC chip; SRAM; radiation hardening; radiation-induced single-event upsets; Error correction; Error correction codes; Latches; Modems; Protection; Radiation hardening; Random access memory; Sequential circuits; Single event upset; Very large scale integration; Radiation-Hardened by Design; SEU; SRAM; Tow-Dimension parity checking;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397372
