Title :
Interconnect synthesis for systems on chip
Author :
Bambha, Neal K. ; Bhattacharyya, Shuvra S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Maryland Univ., College Park, MD, USA
Abstract :
We describe an algorithm for performing a joint scheduling/interconnect synthesis optimization for system-on-chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It is based on a genetic algorithm, and utilizes a graph isomorphism test to significantly pare the search space and increase the search efficiency.
Keywords :
circuit optimisation; genetic algorithms; graph theory; integrated circuit interconnections; multiprocessor interconnection networks; processor scheduling; system-on-chip; SoC; genetic algorithm; graph isomorphism test; interconnect synthesis; joint scheduling; optimization; systems on chip; Computer architecture; Delay; Genetic algorithms; Power system interconnection; Processor scheduling; Routing; Scheduling algorithm; System-on-a-chip; Target tracking; Wires;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Print_ISBN :
0-7695-2182-7
DOI :
10.1109/IWSOC.2004.1319891
