DocumentCode :
3266107
Title :
Network on chip simulations for benchmarking
Author :
Wiklund, Daniel ; Sathe, Sumant ; Liu, Dake
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear :
2004
fDate :
19-21 July 2004
Firstpage :
269
Lastpage :
274
Abstract :
Networks are becoming increasingly popular for use as on-chip interconnects. The problems with specification and performance evaluation increase with these solutions compared to the traditional interconnect. This paper describes the design and simulation environment developed in the SoCBUS network-on-chip project. This environment is used as a basis to develop the benchmarking procedures necessary to assess the performance of the networks. Two benchmarking examples are presented and used for evaluation of the SoCBUS network. These examples show how the simulation environment can be used to find the load bottleneck. They also show the appropriateness of the SoCBUS solution for (hard) real-time systems.
Keywords :
benchmark testing; circuit simulation; integrated circuit design; integrated circuit interconnections; system buses; system-on-chip; SoCBUS; benchmarking; load bottleneck; network-on-chip simulations; on-chip interconnects; performance evaluation; simulation; Bandwidth; Cost function; Delay; Digital signal processing; Network-on-a-chip; Quality of service; Real time systems; Silicon; System-on-a-chip; Time division multiplexing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Print_ISBN :
0-7695-2182-7
Type :
conf
DOI :
10.1109/IWSOC.2004.1319892
Filename :
1319892
Link To Document :
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