VLSI implementation of fast Fourier transformation for OFDM-based high-speed wireless applications

Author

Jiang, Ming ; Yang, Bing ; Fu, Yiling ; Jiang, Anping ; Wang, Xin-An ; Gan, Xuewen ; Zhao, Bayijng ; Zhang, Tianyi

Author_Institution

Sch. of Comput. Sci. & Electr. Eng., Peking Univ., Beijing, China

Volume

3

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1669

Abstract

In this paper, we introduce a fixed-point 16-bit 64 point FFT processor architecture for OFDM-based wireless applications. The processor is based on the DIT (decimation-in-time) radix-2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.

Keywords

OFDM modulation; VLSI; fast Fourier transforms; fixed point arithmetic; logic circuits; low-power electronics; 16 bit; CSA tree; DIT radix-2 butterfly algorithm; OFDM-based high-speed wireless; VLSI; canonical signed digits; constant complex multiplications; decimation-in-time; fast Fourier transformation; fixed-point FFT processor; low power module; Amplitude modulation; Application software; Computer architecture; Decoding; Energy consumption; Hardware; Phase modulation; Quadrature amplitude modulation; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435152

Filename

1435152