ECOMIPS: an economic MIPS CPU design on FPGA

In recently years, many traditional ASIC applications are moving towards a more flexible FPGA based design. To establish a complete application system, it often needs a separate processor to achieve some interactive system functionalities such as I/O operations and control-sensitive tasks. Modern chip producers (Xilinx, Altera, etc) are promoting economic, yet powerful FPGA chips that have the capacity of migrating a general DSP or microprocessor into one FPGA chip. The trend is that both a general CPU module and the application specific circuit are to coexist on a single chip. This article introduces a MIPs CPU architecture or ECOMIPS to be implemented for that purpose. It focuses on economic resource utilization on modern chips (Xilinx Spartan 3 families). Traditional MIPs architecture was modified to avoid resource conflicts with the ASIC part. The key principles of designing such MIPs HDL IP cores are covered and analyzed with implementation results. As a second objective, ECOMIPS also tries to make itself a customizable and reusable architecture for bridging the gap between microprocessor and ASIC.