Multimedia ASIP SoC codesign based on multicriteria optimization

Author

Jeng, I-Horng ; Lai, Feipei ; Naroska, Edwin ; Schwiegelshohn, Uwe

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2001

fDate

2001

Firstpage

342

Lastpage

343

Abstract

This paper shows how to codesign a multimedia ASIP (application specific integrated processor) SoC (system-on-chip) to achieve a low-power and high-throughput goal for a consumer device. The codesign methodology applies Pareto´s multicriteria optimization technique to analyze and partition the software/hardware, the instruction set and the memory hierarchy of an ASIP to provide a flexible approach of finding the best trade-off between conflicting goals based on a given weight function

Keywords

application specific integrated circuits; circuit optimisation; consumer electronics; digital signal processing chips; hardware-software codesign; instruction sets; multimedia systems; Pareto´s multicriteria optimization; application specific integrated processor; consumer electronics; high-throughput consumer device; instruction set; low-power consumer device; memory hierarchy; multicriteria optimization; multimedia ASIP SoC codesign; software/hardware analysis; software/hardware partitioning; system-on-chip; weight function; Application software; Application specific processors; CMOS technology; Design optimization; Instruction sets; Libraries; Multimedia systems; Pareto analysis; Random access memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2001. ICCE. International Conference on

Conference_Location

Los Angeles, CA

Print_ISBN

0-7803-6622-0

Type

conf

DOI

10.1109/ICCE.2001.935337

Filename

935337