A compact hardware accelerator structure for realizing fast IMDCT computation

In this paper, a compact hardware accelerator structure for realizing fast inverse modified discrete cosine transform (IMDCT) computation is proposed. The proposed structure stemmed from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCTIV/DST-IV) decomposition algorithm. After transformation of DST-IV to DCT-IV, the DCT-IV/DCT-IV implementation structure is elaborately manipulated to obtain the compact structure. Compared with the previously reported architecture, the derived structure reduces 2 multipliers (50%), 2 latches (33%) and N/4 memory cells (66%). Meanwhile, the compact structure possesses the same computational efficiency as the previously reported one.