Title :
A compact hardware accelerator structure for realizing fast IMDCT computation
Author :
Li, Hui ; Li, Ping ; Wang, Yiwen
Author_Institution :
State key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
In this paper, a compact hardware accelerator structure for realizing fast inverse modified discrete cosine transform (IMDCT) computation is proposed. The proposed structure stemmed from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCTIV/DST-IV) decomposition algorithm. After transformation of DST-IV to DCT-IV, the DCT-IV/DCT-IV implementation structure is elaborately manipulated to obtain the compact structure. Compared with the previously reported architecture, the derived structure reduces 2 multipliers (50%), 2 latches (33%) and N/4 memory cells (66%). Meanwhile, the compact structure possesses the same computational efficiency as the previously reported one.
Keywords :
digital arithmetic; discrete cosine transforms; compact hardware accelerator structure; discrete sine transform; fast IMDCT computation; inverse modified discrete cosine transform; latches; memory cells; multipliers; Computational complexity; Computational efficiency; Computer architecture; Decoding; Discrete cosine transforms; Discrete transforms; Electron accelerators; Hardware; Laboratories; Thin film devices;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397381
