Title :
An undersampled duty cycle jitter BIST Circuit
Author :
Lim, Kahn Li ; Zilic, Zeljko
Author_Institution :
McGill Univ., Montreal
Abstract :
This paper presents a built-in-self-test (BIST) component that provides an enhancement to existing SerDes BIST measurements of duty cycle jitter. The measurement method provides better accuracy and is scalable due to its all-digital implementation. The BIST was implemented on Altera Stratix FPGA utilizing embedded (phase lock loops) PLLs.
Keywords :
built-in self test; field programmable gate arrays; jitter; phase locked loops; Altera Stratix FPGA; BIST circuit; PLL; SerDes BIST measurements; built-in-self-test component; phase lock loops; Built-in self-test; Circuit testing; Clocks; Field programmable gate arrays; Frequency; Jitter; Microelectronics; Sampling methods; Signal analysis; Transceivers;
Conference_Titel :
Circuits and Systems, 2007. MWSCAS 2007. 50th Midwest Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
978-1-4244-1175-7
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2007.4488570
