Reconfigurable 2.5 GHz phase-locked loop for system on chip applications

2.5 GHz phase-locked loop (PLL) suitable for system-on-the-chip (SOC) implementation is presented. PLL can be configured as a clock multiplication unit (CMU) or as a clock recovery unit (CRU) for data muxing or jitter clean-up applications. It uses a phase-frequency detector (PFD), a low voltage charge-pump, and a low power H-bridge output driver. Phase locked-loop architecture is of Type IV that results in superior performance for power supply rejection ratio (PSRR). The circuit has been implemented in 0.18 μm standard CMOS process, occupies 1230 μm by 248 μm and dissipates 128 mW from a 1.8V power supply.