DocumentCode :
3266300
Title :
Software FIFO based interconnection between DSP and FPGA in video encoding system
Author :
Ji, Xiaonan ; Jiang, Hongxu ; Xiao, Chaosheng ; Wang, Yuanpeng
Author_Institution :
Digital Media Lab., Beihang Univ., Beijing, China
Volume :
8
fYear :
2010
fDate :
16-18 Oct. 2010
Firstpage :
3699
Lastpage :
3702
Abstract :
In video encoding hardware system based on camera link interface, in order to coordinate data transmission between different clock domains, we designed a DSP and FPGA interconnection scheme, in which a software FIFO was used. This article introduced relevant interface interconnects and timing analysis. The system we are using proved the method introduced in the article is stable and efficient to guarantee the speed and correctness of data transmission.
Keywords :
field programmable gate arrays; timing; video coding; DSP; FPGA; camera link interface; clock domains; data transmission; software FIFO based interconnection; timing analysis; video encoding hardware system; video encoding system; Digital signal processing; Field programmable gate arrays; Random access memory; Software; Streaming media; Synchronization; DSP; FIFO; FPGA; timing control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Image and Signal Processing (CISP), 2010 3rd International Congress on
Conference_Location :
Yantai
Print_ISBN :
978-1-4244-6513-2
Type :
conf
DOI :
10.1109/CISP.2010.5647310
Filename :
5647310
Link To Document :
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