Real-time implementation of full-search vector quantization on a low memory SIMD architecture

Abstract only given. A significant amount of current research on vector quantization (VQ) implementations addresses increasing the speed of image encoding. This is typically accomplished by imposing structures, exploiting properties of the distance measure, or developing efficient and fast implementations. This research proposes a parallel implementation of a full-search VQ encoding algorithm using a low memory, fine grain SIMD pixel processor (SIMPil) being developed at Georgia Tech. This implementation fully exposes the available parallelism of the encoding process and exploits the processing and I/O capabilities of the processor, resulting in a system that can perform real-time image and video compression. The proposed implementation encodes a large region of the original image at once, replacing each constituent input block with its corresponding VQ codeword index. Preliminary simulation results indicate that the proposed implementation is capable of sustain real-time frame rates. In the simulation, 92058 clock cycles are required to encode a single 64×64 region. The image of Lena (256×256) requires 16 passes to be completely encoded, for a total of about 1472089 clock cycles. With a 50 MHz processor, a 256×256 image frame will be encoded in 29.4 ms, supporting a frame rate of >30 frames/sec. Three VQ implementations are compared on different hardware platforms. A prototype SIMPil implementation is being fabricated by MOSIS in 0.8 μm CMOS