Title :
FPGA implementation of a modified hard decision decoding for 2-D TPC
Author :
Zhi, Zhong ; Shan Mingguang ; Weiwei, Zhang ; Yang Bowen ; Hao Bengong ; Ren Guanghui
Author_Institution :
Inf. & Commun. Eng. Coll., Harbin Eng. Univ., Harbin, China
Abstract :
A modified algorithm for two-dimensional TPC decoding is proposed to reduce the wrong frame rate in the (16,11,4)2 Turbo Product Code (TPC) decoding in this paper. It is based on the hard decision decoding, including a chooser and a parallel decoding architecture that one is column-row and the other is row-column. The Monte-Carlo simulation shows that 30% wrong frame is eliminated and the implementation of the decoder for TPC (16,11,4)2 with FPGA has achieved the decoding throughput of 53 Mbit/s with 20 M clock.
Keywords :
Monte Carlo methods; field programmable gate arrays; product codes; turbo codes; 2D TPC; FPGA implementation; Monte-Carlo simulation; modified hard decision decoding; turbo product code; Clocks; Delay; Educational institutions; Field programmable gate arrays; Hardware; Iterative decoding; Parallel architectures; Product codes; Throughput; Two dimensional displays; Decoder; FPGA; Hard decision decoding; TPC;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397405
