Title :
Design of a configurable fixed-point multiplier for digital signal processor
Author :
Zhang, Xinyue ; Li, Zhaolin ; Zheng, Qingwei
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A configurable fixed-point multiplier for digital signal processing (DSP) applications is proposed in this paper. It is implemented in four pipeline stages. The proposed multiplier supports multiple-precision operations, including one 32×32, two 16×32, two 16×16 or four 8×8 signed/unsigned multiplication operations and 16-bit or 8-bit dot product/double dot product operations. It is modeled in VerilogHDL and synthesized in 0.13 ¿m CMOS technology. The critical path delay of the proposed design is 1.69 ns.
Keywords :
digital arithmetic; digital signal processing chips; hardware description languages; CMOS technology; The critical path; VerilogHDL; configurable fixed-point multiplier; digital signal processing application; digital signal processor; double dot product operation; multiple-precision operation; multiplication operation; pipeline stages; CMOS technology; Digital signal processing; Digital signal processors; Information science; Information technology; Laboratories; Microelectronics; Parallel processing; Pipelines; Signal design;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397407
