Architecture of a configurable Centered Discrete Fractional Fourier Transform processor

This paper presents a novel, configurable architecture for real-time computation of the centered discrete fractional Fourier transform (CDFRFT). The proposed architecture exploits the advantages of both spatial and temporal parallelism in computing the N point CDFRFT of N equally spaced fractional domains in between time and frequency, where N is an integer power of 2. A detailed study of the hardware complexity and the implementation details have been achieved through HDL synthesis, timing analysis and resource utilization. Further, to validate the architecture, it has been implemented on a Xilinx FPGA.