High throughput LDPC decoder architecture for DVB-S2

This paper proposed a new decoder architecture which employs HSS algorithm and simple check node update algorithm. Memory architecture is a major point of in terms of high speed and area of implementation, therefore the efficient memory design to accelerate decoding throughput is studied. In conventional decoder architectures, p- parallelism, dc-serialism, and q-serialism are required. This paper attempted memory division to obtain dc-parallelism and memory sharing to reduce area, 7 times of decoder throughput may be improved compared to conventional one.