DocumentCode :
3266892
Title :
A 1.2V 10bit 83MSps pipeline ADC in 130nm CMOS
Author :
Meng, Hao ; Sun, Jia ; Paasio, Ari
Author_Institution :
Turku Center for Comput. Sci. (TUCS), Microelectron. Lab., Turku, Finland
fYear :
2009
fDate :
19-21 Jan. 2009
Firstpage :
177
Lastpage :
180
Abstract :
A 1.2 V 10 bit 83 MS/s pipeline ADC implemented in 130 nm CMOS Technology is described. Emphasis was placed on noise analysis and capacitance optimization. Experience of operational amplifier, comparator and switch design were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33 LSB respectively, while SNDR is 57.7 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS technology; analogue-digital conversion; capacitance optimization; comparator; complementary metal-oxide-semiconductor; noise analysis; operational amplifier; size 130 nm; switch design; voltage 1.2 V; CMOS technology; Capacitance; Clocks; Communication switching; Integrated circuit technology; Operational amplifiers; Pipelines; Redundancy; Sampling methods; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
Type :
conf
DOI :
10.1109/PRIMEASIA.2009.5397417
Filename :
5397417
Link To Document :
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