Title :
Circuit technologies for a 12 ns 4 Mb TTL BiCMOS DRAM at 3.3 V operation
Author :
Yokoyama, Y. ; Nakagawa, K. ; Akiyama, N. ; Ohta, T. ; Someya, T. ; Tamba, A. ; Miyazawa, H. ; Miyazawa, K. ; Murata, J. ; Kobayashi, Y.
Author_Institution :
Hitachi, Ltd., Ibaraki, Japan
Abstract :
Circuit technologies are described for a 4-Mb transistor-transistor logic (TTL) BiCMOS DRAM with a 12-ns access time. Successful 3.3-V operation is reported. New circuit technologies, such as a dynamic pull-up input buffer, a common drain BiNMOS decoder, and a direct bootstrap and two-level precharge architecture of the TTL output buffer, make it possible to realize fast access DRAMs. Detailed circuit descriptions of the input buffer and decoder and output buffer are provided, together with a tabular design summary.<>
Keywords :
BiCMOS integrated circuits; DRAM chips; VLSI; transistor-transistor logic; BiCMOS DRAM; TTL output buffer; ULSI; access time; circuit descriptions; circuit technologies; common drain BiNMOS decoder; decoder; direct bootstrap; dynamic pull-up input buffer; fast access DRAMs; input buffer; output buffer; tabular design summary; two-level precharge architecture; BiCMOS integrated circuits; Bipolar transistors; Decoding; Delay effects; FETs; Laboratories; Large scale integration; Logic gates; Low voltage; Random access memory;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229239
