Title :
ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers
Author :
AlJuffri, Abdullah A. ; AlNahdi, Mohammed M. ; Hemaid, Anas A. ; AlShaalan, Osamh A. ; BenSaleh, Mohammed S. ; Obeid, Abdulfattah M. ; Qasim, Syed Manzoor
Author_Institution :
Nat. Center for Electron. & Photonics Technol., King Abdulaziz City for Sci. & Technol., Riyadh, Saudi Arabia
Abstract :
Finite impulse response (FIR) filter is widely used in digital signal processing (DSP) and communication systems. Multiplication is an essential and complex building block used in the realization of FIR filters. In this paper, Wallace tree and Vedic multipliers are used for efficient realization of sequential and parallel scalable microprogrammed FIR filter architectures. The designs are coded in Verilog hardware description language and realized using LFoundry 150nm standard-cell based technology. ASIC realization results are presented and analyzed in order to evaluate the performance of both FIR filters.
Keywords :
FIR filters; application specific integrated circuits; digital signal processing chips; hardware description languages; logic design; multiplying circuits; ASIC realization; DSP; LFoundry standard-cell based technology; Vedic multipliers; Verilog hardware description language; Wallace tree; communication systems; digital signal processing; finite impulse response filter; scalable microprogrammed FIR filter architectures; size 150 nm; Adders; Application specific integrated circuits; Delays; Digital signal processing; Finite impulse response filters; Hardware; Hardware design languages; ASIC Design; FIR Filter; Vedic Mathematics; Wallace Tree; microprogrammed; multiplier;
Conference_Titel :
Environment and Electrical Engineering (EEEIC), 2015 IEEE 15th International Conference on
Conference_Location :
Rome
Print_ISBN :
978-1-4799-7992-9
DOI :
10.1109/EEEIC.2015.7165480
