DocumentCode
3267128
Title
A low-power variable-length FFT processor base on Radix-24 algorithm
Author
Lu, Qingwang ; Wang, Xin An ; Niu, JiuChong
Author_Institution
Key Lab. of Integrated Microsyst. Sci. & Eng. Applic., Peking Univ., Shenzhen, China
fYear
2009
fDate
19-21 Jan. 2009
Firstpage
129
Lastpage
132
Abstract
A low-power variable-length FFT processor is proposed in this paper. Mixed-radix algorithm and Radix-24 single path delay feedback (SDF) pipeline architecture are chosen to achieve low computation complexity and high reconfigurable flexibility. The system can be reconfigured as 16, 32, 64, 128, 256, 512, 1024, 2048 or 4096-points FFT. The FFT processor is implemented with SMIC 0.18 ¿m CMOS technology. The core area is 4 mm2. Compared with other design, the proposed FFT processor consumes lower power and smaller area due to adopting high radix algorithm.
Keywords
CMOS digital integrated circuits; fast Fourier transforms; pipeline arithmetic; Radix-24 single path delay feedback pipeline architecture; SMIC CMOS technology; fast Fourier transform; low-power variable-length FFT processor; mixed-radix algorithm; radix-24 algorithm; size 0.18 mum; Algorithm design and analysis; CMOS technology; Communication standards; Computer architecture; Delay; Energy consumption; Frequency estimation; Hardware; OFDM; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location
Shanghai
Print_ISBN
978-1-4244-4668-1
Electronic_ISBN
978-1-4244-4669-8
Type
conf
DOI
10.1109/PRIMEASIA.2009.5397429
Filename
5397429
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