DocumentCode
3267180
Title
A novel D-latch in multiple-valued semi-floating-gate recharged logic
Author
Mirmotahari, Omid ; Berg, Yngvar
Author_Institution
Dept. of Informatics, Oslo Univ., Norway
fYear
2004
fDate
19-22 May 2004
Firstpage
210
Lastpage
213
Abstract
In this paper, we present several different proposals for implementing a multiple-valued (MV) semi-floating-gate (SFG) D-latch. This paper aims to illustrate the advantages and disadvantages of each approach. Measurements from a fabricated chip in a 0.6 μm CUP process is included for verifying the detailed arguments.
Keywords
flip-flops; multivalued logic circuits; 0.6 micron; CUP process; SFG D-latch; multiple-valued logic; semi-floating-gate recharged logic; Informatics; Inverters; Joining processes; Logic design; Logic devices; Logic programming; Nonvolatile memory; Proposals; Semiconductor device measurement; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on
ISSN
0195-623X
Print_ISBN
0-7695-2130-4
Type
conf
DOI
10.1109/ISMVL.2004.1319943
Filename
1319943
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