• DocumentCode
    3267203
  • Title

    Comparing simulations and graphical representations of complexities of benchmark and large-variable circuits

  • Author

    Prasad, P.W.C. ; Beg, Azam ; Singh, Ashutosh Kumar

  • Author_Institution
    Sydney Study Centre, Charles Sturt Univ., Sydney, NSW, Australia
  • Volume
    5
  • fYear
    2010
  • fDate
    22-24 June 2010
  • Abstract
    In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.
  • Keywords
    Boolean functions; binary decision diagrams; benchmark circuits; binary decision diagrams; graphical representations; large-variable circuits; randomly generated Boolean function complexity; Area measurement; Binary decision diagrams; Boolean functions; Circuit simulation; Circuit testing; Computational modeling; Design automation; Digital circuits; Logic testing; Predictive models; Area Complexity; Benchmark circuits; Binary Decision diagram;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Education Technology and Computer (ICETC), 2010 2nd International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-6367-1
  • Type

    conf

  • DOI
    10.1109/ICETC.2010.5529799
  • Filename
    5529799