Comparator-based successive folding ADC

Author

Chio, V-Fat ; Choi, HOll-Lon ; Chan, Chi-Hang ; Wong, Si-Seng ; Sin, Sai-Weng ; Seng-Pan U ; Martins, R.P.

Author_Institution

Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao, China

fYear

2009

fDate

19-21 Jan. 2009

Firstpage

117

Lastpage

120

Abstract

A 4-bit 1-GS/s ADC with a comparator-based successive folding (CSF) architecture is presented. Residue pre-charging and successive folding techniques are proposed for the CSF ADC to enhance quantization speed and achieve less complexity, leading to high power efficiency. Simulation results show that the ADC obtains a SNDR of 23.7 dB at Nyquist input frequency and consumes 430 Â¿W from a 1 V supply in 65 nm CMOS, yielding a FOM of 34 fJ per conversion step.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); logic design; CMOS integrated circuits; Nyquist input frequency; analogue-digital converters; comparator-based successive folding ADC; power 430 muW; quantization speed; residue pre-charging; size 65 nm; voltage 1 V; word length 4 bit; Electronic mail; Energy resolution; Frequency conversion; Laboratories; Output feedback; Quantization; Sampling methods; Silicon compounds; Very large scale integration; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-4668-1

Electronic_ISBN

978-1-4244-4669-8

Type

conf

DOI

10.1109/PRIMEASIA.2009.5397434

Filename

5397434