Title :
A 333 MHz, 72 Kb BiCMOS pipelined buffer memory with built-in self test
Author :
Yokomizo, K. ; Naito, K.
Author_Institution :
Oki Electr. Ind. Co. Ltd., Tokyo, Japan
Abstract :
The designs for a high-speed BiCMOS buffer memory and a high-speed BIST circuit are studied. A BiCMOS pipelined read architecture constructed using a latched ECL sense amplifier and a clocked ECL-CMOS level converter is proposed, and a BiCMOS complimentary clocked driver technique is described. The memory is constructed with 0.8- mu m technology and achieves 333-MHz operating frequency in simulation. It is confirmed that the BIST circuit, using linear feedback shift registers (LFSRs), can examine the memory at maximum operating frequency without degradation in the speed performance of the memory.<>
Keywords :
BiCMOS integrated circuits; VLSI; buffer storage; built-in self test; circuit analysis computing; emitter-coupled logic; 0.8 micron; 333 MHz; 72 Kbit; BIST circuit; BiCMOS; LFSRs; built-in self test; clocked ECL-CMOS level converter; complimentary clocked driver; latched ECL sense amplifier; linear feedback shift registers; operating frequency; pipelined buffer memory; pipelined read architecture; simulation; Automatic testing; BiCMOS integrated circuits; Built-in self-test; Circuit simulation; Clocks; Frequency; Research and development; Switches; System testing; Very large scale integration;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229250
