Title :
New decoding architecture to reduce peak current and its implementation to 4 M ECL SRAM
Author :
Ohba, A. ; Sato, H. ; Hirose, T. ; Hosogane, A. ; Honda, K. ; Kohno, Y. ; Anami, K.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The authors describe the multitiming buffering architecture (MTBA) and the pseudo hierarchical word decoding architecture (pseudo-HWD). These architectures have been implemented on a 4M emitter-coupled logic (ECL) SRAM with a 0.6- mu m BiCMOS process, and have effectively reduced the peak current of the decoding circuit by 32% and maximum di/dt by 63%, as compared with the three-level HWD. The SRAM achieved a 7-ns access time and a 160-mA active current at 50 MHz.<>
Keywords :
BiCMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; 0.6 micron; 160 mA; 4 Mbit; 50 MHz; 7 ns; BiCMOS; ECL; SRAM; access time; active current; decoding circuit; maximum di/dt; multitiming buffering architecture; peak current reduction; pseudo hierarchical word decoding architecture; BiCMOS integrated circuits; Capacitance; Circuit noise; Decoding; Delay; Large scale integration; Power supplies; Random access memory; Switches; Timing;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229251
