On Increasing the Computational Efficiency of Long Integer Multiplication on FPGA

This paper presents a compact hardware architecture for long integer multiplication and proposes a strategy to increase the computational efficiency of the Karatsuba algorithm on FPGA. The presented architecture aims to provide an efficient and compact architecture to be used where long integer multiplication is definitely required such as Cryptography, especially Public Key Cryptography (PKC), Coding theory, DSP and many more. There are several studies in the literature related to increase the efficiency of multiplication, especially in public key cryptography. From our point of view, the main advantage of this method over other existing methods is that recursive utilization of hardware resources with tight scheduling brings better performance with smaller logic area. Our coprocessor is also suitable for multiplications of polynomials in GF(p) and GF(2k). Our method achieves highest available frequency of FPGA. We compare our hardware performance figures for different bit width multiplication with other reported studies. The results show that our architecture combines performance with small area size.