Title :
A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier
Author :
Seki, T. ; Itoh, E. ; Furukawa, C. ; Maeno, I. ; Ozawa, T. ; Sano, H. ; Suzuki, N. ; Matsukawa, Y.
Author_Institution :
Fujitsu VLSI Ltd., Kasugai, Japan
Abstract :
A 1-Mb (256 K*4) SRAM with an access time of 6 ns using a 0.5- mu m CMOS technology is described. Fast access and low power dissipation are achieved by using a new nMOS source-controlled latched sense amplifier and a data output pre-reset circuit that reduces the output transition time.<>
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; 0.5 micron; 1 Mbit; 6 ns; CMOS; SRAM; access time; data output pre-reset circuit; fast access time; nMOS source-controlled latched sense amplifier; output transition time; power dissipation; CMOS process; CMOS technology; Delay; Driver circuits; Inverters; MOS devices; Pulse amplifiers; Random access memory; Very large scale integration; Voltage;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229253
