Title :
Serial 9 Mb flash EEPROM for solid state disk applications
Author :
Mehrotra, S. ; Yuan, J.H. ; Cernea, R.A. ; Chien, W.Y. ; Guterman, D.C. ; Samachisa, G. ; Norman, R.D. ; Mofidi, M. ; Lee, W. ; Fong, Y. ; Mihnea, A. ; Harari, E. ; Gregor, R.W. ; Eberhardt, E.P. ; Radosevich, J.R. ; Stiles, K.R. ; Kohler, R.A. ; Leung, C
Author_Institution :
SunDisk Corp., Santa Clara, CA, USA
Abstract :
A 9-Mb flash EEPROM incorporating a serial interface and other features specifically suited for low-cost, high-capacity, low-power solid-state storage systems has been fabricated using a triple polysilicon, single-metal, 0.9- mu m CMOS process. Thin oxide transistors are used for low read and programming voltages, and thick oxide transistors are used for high erase voltage. The memory array utilizes a virtual ground architecture. The cell erases using inter-poly dielectric tunneling and programs using channel hot electron injection. The use of a split channel memory transistor allows the floating gate portion of the cell to be erased to negative thresholds, thus eliminating the over-erase limitation of traditional stacked gate flash cells.<>
Keywords :
CMOS integrated circuits; EPROM; VLSI; 0.9 micron; 9 Mbit; CMOS; channel hot electron injection; features; flash EEPROM; floating gate; high erase voltage; high-capacity; inter-poly dielectric tunneling; low-cost; low-power solid-state storage systems; programming voltages; serial interface; single-metal; solid state disk applications; split channel memory transistor; thick oxide transistors; thin oxide transistors; triple polysilicon; virtual ground architecture; Access protocols; CMOS process; Clocks; Costs; Delay; EPROM; Registers; Solid state circuits; Tunneling; Voltage;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229254
