A new decoding scheme and erase sequence for 5 V only sector erasable flash memory

Author

Nakayama, T. ; Kobayashi, S. ; Miyawaki, Y. ; Futatsuya, T. ; Terada, Y. ; Ajika, N. ; Yoshihara, T.

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

fYear

1992

fDate

4-6 June 1992

Firstpage

22

Lastpage

23

Abstract

The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.<>

Keywords

EPROM; MOS integrated circuits; PLD programming; VLSI; 10 V; 5 V; 5 V only memory; 64 Mbit; ULSI; decoding scheme; erase sequence; erased memory cells; power consumption; programming after erase; sector-erasable flash memory; source line decoder; switching voltage; threshold voltage distribution; word line pitch; Breakdown voltage; Circuit testing; Energy consumption; Flash memory; Fluctuations; Iterative decoding; Laboratories; Large scale integration; Parameter estimation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Conference_Location

Seattle, WA, USA

Print_ISBN

0-7803-0701-1

Type

conf

DOI

10.1109/VLSIC.1992.229255

Filename

229255