Designing with high speed clock drivers

Today´s high speed systems are encountering problems with clocking that were not considerations with lower speed clocks and systems. These problems are forcing the design community to rethink the task of clock distribution to avoid the consequences of the higher speeds. As a result, new products and new design techniques are being introduced which circumvent the complications of the order systems. The consequences of poor clock design fall into two categories, skew and noise, each of which has its associated problems. Those related to skew include misclocking (reverse clocking) of pipelined registers, duty cycle distortion, and erosion of the usable portion of the clock period. Noise related problems that can develop include signal reflections (termination problems), ground bounce, EMI, cross coupling of signals, and double clocking. The solution to many clocking problems is to distribute the clock in a star pattern by taking a single clock signal and fanning it out with a low skew clock driver or buffer. This way each clock input or lumped load has its own individual clock line that is matched to every other clock line from the same source. By using a low skew clock driver/buffer, the designer can carefully distribute his clock while minimizing skew and controlling signal quality