Title :
Three dimensional multiple valued circuits design based on single-electron logic
Author :
Yanushkevich, S.N. ; Shmerko, V.P. ; Guy, L. ; Lu, D.C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
The three-dimensional (3D) model of a multiple valued network, based on a hypercube-like topology, is proposed. A graph embedding technique is used to design hypercube based structures. It is shown that the hypercube-like topology is a single-electron transistor (SET) technology-oriented solution to the implementation of multiple-valued networks.
Keywords :
decision diagrams; decision trees; hypercube networks; logic design; multivalued logic circuits; network topology; single electron transistors; 3D multiple valued circuits; N-hypercube interconnection network; SET logic; decision trees; graph embedding technique; hypercube based structures; hypercube-like topology; multiple-valued decision diagram techniques; multiple-valued networks; nanoelectronic devices; single-electron transistor technology; Circuit synthesis; Data structures; Decision trees; Design methodology; Hypercubes; Josephson junctions; Logic circuits; Logic design; Network topology; Space technology;
Conference_Titel :
Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on
Print_ISBN :
0-7695-2130-4
DOI :
10.1109/ISMVL.2004.1319954
