Title :
A 66-MHz configurable secondary cache controller with primary cache copyback support
Author :
Reed, P. ; Alexander, M. ; Beavers, B. ; Evers, R. ; Gary, S. ; Gerosa, G. ; Grossman, A. ; Gutierrez, C. ; Jackson, G. ; Kearney, M. ; Lewelling, R. ; Slaton, J. ; Stanphill, R.
Author_Institution :
Motorola Microprocessor Group, Austin, TX, USA
Abstract :
The authors describe a 66-MHz secondary cache controller which supports a primary cache operating in copyback mode. The device integrates a 278-kb direct-mapped cache tag array plus control logic to provide full multiprocessing capability and is configurable to support cache sizes from 256 kbytes to 1 Mbyte. Implemented in a 0.8- mu m twin-well double-poly triple-metal CMOS process, the device uses a high-resistivity poly load memory cell to achieve high density.<>
Keywords :
CMOS integrated circuits; VLSI; buffer storage; microcontrollers; storage management; 0.8 micron; 256 kbyte to 1 Mbyte; 278 kbit; 66 MHz; CMOS; configurable secondary cache controller; control logic; copyback mode; direct-mapped cache tag array; double-poly; high density; high-resistivity poly load memory cell; multiprocessing capability; primary cache copyback support; triple-metal; twin-well CMOS; CMOS logic circuits; CMOS process; Clocks; Conductivity; Control systems; Logic arrays; Logic devices; Microprocessors; Random access memory; Size control;
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
DOI :
10.1109/VLSIC.1992.229258
