Title :
Optimal transformation of non-tree topologies for timing analysis
Author :
Chen, Zhi-Wei ; Yan, Jin-Tai
Author_Institution :
Inst. of Eng. & Sci., Chung-Hua Univ., Hsinchu, Taiwan
Abstract :
Based on the assumption of a single wiring open in a signal net, it is known that the non-tree topology for a signal net has no adjacent loop. In this paper, based on RC non-tree transformation in Elmore delay model, an optimal algorithm for timing analysis is firstly proposed to compute the timing delays of all the reference nodes in a non-tree topology. Compared with the SPICE tool, the experimental results show that our proposed approach uses less CPU time to achieve the timing results for non-tree topologies under 0.62% delay error on the average.
Keywords :
RC circuits; delays; network topology; timing; wiring; Elmore delay model; RC nontree transformation; SPICE tool; delay error; nontree topology; optimal transformation; reference nodes; signal net; single wiring; timing analysis; timing delays; Capacitance; Delay; Joining processes; Network topology; Protection; Reliability engineering; Routing; Signal analysis; Timing; Wiring;
Conference_Titel :
Microelectronics & Electronics, 2009. PrimeAsia 2009. Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4668-1
Electronic_ISBN :
978-1-4244-4669-8
DOI :
10.1109/PRIMEASIA.2009.5397446