DocumentCode
3267475
Title
A polynomial time algorithm for non-disjoint decomposition of multiple-valued functions
Author
Dubrova, Elena
Author_Institution
IMIT/KTH, R. Inst. of Technol., Stockholm, Sweden
fYear
2004
fDate
19-22 May 2004
Firstpage
309
Lastpage
314
Abstract
This paper addresses the problem of non-disjoint decomposition of multiple-valued functions. First, we show that the problem of computing non-disjoint decompositions of a multiple-valued function is related to the problem of finding multiple-vertex dominators of a logic circuit, representing the function. Second, we present an O(nk) algorithm for computing all multiple-vertex dominators of a fixed size k, where n is the number of gates of the logic circuit. Our result is important because no polynomial-time algorithm for finding all possible non-disjoint decompositions of multiple-valued functions is known. The presented approach allows us computing a certain subset of non-disjoint decompositions (all reflected in a given circuit structure) in polynomial time. A set of experiments on benchmark circuits illustrates the efficiency of our approach.
Keywords
logic design; multivalued logic circuits; polynomials; logic circuit multiple-vertex dominators; multiple-valued function nondisjoint decomposition; polynomial time algorithm; Boolean functions; Circuit synthesis; Field programmable gate arrays; Formal verification; Logic circuits; Logic testing; Polynomials; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on
ISSN
0195-623X
Print_ISBN
0-7695-2130-4
Type
conf
DOI
10.1109/ISMVL.2004.1319960
Filename
1319960
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