DocumentCode :
3267555
Title :
Low power on-chip supply voltage conversion scheme for 1G/4G bit DRAMs
Author :
Takashima, D. ; Watanabe, S. ; Fuse, T. ; Sunouchi, K. ; Hara, T.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fYear :
1992
fDate :
4-6 June 1992
Firstpage :
114
Lastpage :
115
Abstract :
A new low power on-chip supply voltage conversion scheme is proposed. This scheme connects two or more DRAMs in series to make up for the large gap between the external and internal supply voltages. As large as a 50% power dissipation reduction has been successfully verified using the test system. This device is seen to be promising for voltage conversion in forthcoming gigabit DRAMs.<>
Keywords :
DRAM chips; convertors; power supply circuits; 1 Gbit; 4 Gbit; DRAMs; external supply voltage; internal supply voltages; low power on-chip supply voltage conversion scheme; power dissipation reduction; test system; Circuits; Clocks; Fuses; Power dissipation; Power supplies; Random access memory; Timing; Ultra large scale integration; Variable structure systems; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-0701-1
Type :
conf
DOI :
10.1109/VLSIC.1992.229265
Filename :
229265
Link To Document :
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